For solder flip chip assembly of a first level package or device, the solder interconnects are formed by joining solder bumps on the chip with solder bumps on the substrate. The solder bumps on the substrate help compensate for chip bump height variations and substrate warpage. Flip chip technology allows the largest numbers of inputs/outputs (“I/Os”) for the smallest footprint of the chip. This enables manufacturing small packages known in the art as chip-scale packages.
IBM introduced this technology in the early 1960's with the solid logic technology in their IBM System/360™. It extended interconnection capabilities beyond existing wire-bonding techniques, allowing the area array solder-bump configuration to extend over the entire surface of the chip (die) providing solder bumps for interconnection to a substrate by the so-called “C4” process. This allowed for the highest possible I/O counts to meet the increasing demand for electrical functionality and reliability in IC technology. “C4” comprises the term for describing the process of connecting semiconductor and other devices, also known as the IBM “flip chip” or “controlled collapse chip connection,” from which the industry derives the acronym “C4.” The devices that employ C4 technology comprise integrated circuits (“IC” chips), passive filters, detector arrays and microelectromechanical systems (“MEMS”) all of which are well known in the art. The present invention comprises processes used in the manufacturing of these devices, and the products obtained by these processes.
The C4 process interconnects devices to external circuitry by means of solder bumps that have been deposited on semiconductor chip pads or metal substrates. In order to mount the chip to external circuits such as a circuit board or another chip or a wafer used in manufacturing other chips, a chip having solder bumps is flipped over so that the solder is aligned with matching connecting sites (e.g., connector pads) on an external circuit, and the connection completed by raising the temperature of the solder so that it flows and adheres to the connecting sites. In these applications, the chip may be made of conventional semiconductor materials known in the art or compound semiconductor materials (e.g., GaAs, HgCdTe, InP, etc) attached to CMOS readout circuits through very high density Indium Micro Bump Arrays.
Oxidation of substrates, however, causes problems with solder adhesion. Systems Equipment Technology (“SET”) along with other manufacturers of bonding equipment address the issue, noting oxides generally adhere poorly to other metals or oxides which causes defects in chip manufacture. The bonding force employed in the manufacturing process must be sufficient to cause penetration of the oxide to achieve metal-to-metal cohesion or adhesion. Not only do the oxides increase the required bonding force, but they may also raise the electrical resistance of the joint. Even after the device has been bonded, existing oxides may provide a convenient site for further oxidation, leading to reliability and performance problems.
The industry recognizes breaking through the oxide can be performed by mechanical scrubbing, but this process is only effective with large bumps at loose alignment tolerances. An alternative solution is to use liquid flux to reduce the oxide, but this requires an additional cleaning step to remove flux residues which becomes very difficult at small gaps between dies.
They go on to note that high quality and reliable bonding often require an oxygen free environment to prevent oxide formation during the bonding sequence at elevated temperature. Some materials in the chip assembly such as Indium form oxides at room temperature which must also be removed before bonding for the same reasons. The need to remove and prevent oxides in situ to achieve proper joining therefore becomes apparent, especially where the chip is made of compound semiconductor materials as noted above.
SET has developed a substrate chuck and a bond head with a localized confinement chamber which operates safely with reducing gases such as forming gas or formic acid vapor. This configuration has been successfully implemented on SET bonder models FC.150 and FC300, a chip/wafer bonding apparatus or C4NP transfer tool.
To preserve the standard capabilities of their hybridization equipment and especially the low contact force measurement applied to the components, SET has developed a “semi-open” confinement chamber with no hardware sealing. A non-contact virtual seal is used to ensure gas collection and prevent oxygen intrusion.
The principle of the SET virtually sealed confinement chamber consists of a non-contact virtual seal of the micro-chamber to enable gas confinement for chip-to-chip or chip-to-wafer bonding under controlled atmosphere while preserving the alignment of the device with respect to its substrate. The process employs a chip-to-chip or a chip-to-wafer configuration in which the process gas is injected through horizontal nozzles towards the device being bonded; an exhaust ring removes the process gas from the micro-chamber and into the gas exhaust line, keeping the gas out of the machine and the clean room; a nitrogen curtain formed around the exhaust, ensuring that ambient air is not entrained into the micro-chamber by the Venturi effect; and a cover attached to the bond head to create a confined micro-chamber.
This configuration of the SET apparatus enables two operation modes: first, an inert gas such as nitrogen to prevent oxide formation on bonding surfaces during the bonding sequence; second, a forming gas such as gaseous formic acid is employed to remove and prevent oxide formation prior to bonding, thus ensuring good wetting and high quality solder joints. This is well-suited for applications using Indium. This confinement chamber can be used with pure nitrogen, nitrogen saturated with formic acid vapor or process gases. The gas saturation is adjustable to meet the process requirements and provide high quality and reliable bonding; allows for reduced bonding forces and temperatures due to oxide-free surfaces; eliminates the need for other cleaning steps with flux-less bonding; and provides higher yield and reliability by thorough removal of oxides.
During the process however, it is difficult to track the effective distribution of the reducing gas such as formic acid since the working gap between the metal substrate such as copper and the device is very small.
Accordingly, it is desirable to have a process or a way to follow the distribution of the reducing gas.